Method of forming an interconect structure of a semiconductor device

ABSTRACT

A method of forming a semiconductor device structure is disclosed. First and second etch stop layers are formed overlying a semiconductor structure having a conductive feature formed therein. A dielectric layer is formed overlying the second etch stop layer, and a hard mask, that comprises a tungsten-based material, is formed overlying the dielectric layer, and patterned. A resist layer is formed over the patterned hard mask. Using the patterned resist layer as a mask, a first etching process is performed to form a via opening that extends partially through the dielectric layer. Using the patterned hard mask as an etch mask, a second etching process (e.g., dry etching process) is performed to extend the via opening through the second etch stop layer, and a third etching process (e.g., wet etching process) is performed to extend the via opening through the first etch stop layer to reach the conductive feature.

BACKGROUND

The fabrication of integrated circuits can be broadly separated into twomain sections, front-end-of-the-line (FEOL) fabrication andback-end-of-the-line (BEOL) fabrication. FEOL fabrication includes theformation of devices (e.g., transistors, capacitors, resistors, etc.)within a semiconductor substrate. BEOL fabrication includes theformation of one or more metal interconnect layers comprised within oneor more insulating dielectric layers disposed above the semiconductorsubstrate. The metal interconnect layers of the BEOL electricallyconnect individual devices of the FEOL to external pins of an integratedchip.

Technological advances in IC materials and design have producedgenerations of ICs. Each generation has smaller and more complexcircuits than the previous generation. In the course of IC evolution,functional density (i.e., the number of interconnected devices per chiparea) has generally increased while geometric size (i.e., the smallestcomponent (or line) that can be created using a fabrication process) hasdecreased. This scaling-down process generally provides benefits byincreasing production efficiency and lowering associated costs.

As feature sizes continue to decrease, fabrication processes continue tobecome more complex, especially with decreasing lithographic featuresizes, decreasing critical dimensions of features and decreasing pitchbetween features. Therefore, it is a challenge to form reliablesemiconductor devices at smaller and smaller sizes.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a flowchart of a method of forming an interconnect structureof a semiconductor device structure in accordance with some embodiments.

FIGS. 2A-2N are cross-sectional views of various stages of a process forforming an interconnect structure of a semiconductor device structure inaccordance with some embodiments.

FIG. 3 is a cross-sectional view that illustrates differentback-end-of-line interconnect layers of an integrated circuitarchitecture where interconnect structures fabricated in accordance withFIGS. 1 and 2A-2N may be integrated in accordance with some embodiments.

DETAILED DESCRIPTION

The present disclosure relates generally to semiconductor structures,and more particularly, to interconnect structures and methods of forminginterconnect structures.

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

It should be understood that, although the terms first, second, thirdetc. may be used herein to describe various elements, components,regions, layers, portions and/or sections, these elements, components,regions, layers, portions and/or sections should not be limited by theseterms. These terms are only used to distinguish one element, component,region, layer, portion or section from another region, layer or section.Thus, a first element, component, region, layer, portion or sectiondiscussed below could be termed a second element, component, region,layer, portion or section without departing from the teachings of thepresent disclosure.

Further, spatially relative terms, such as “beneath,” “below,” “under,”“lower,” “above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation illustrated inthe figures. For example, if the device in the figures is turned over,elements described as being “below” or “beneath” other elements orfeatures would then be oriented “above” the other elements or features.Thus, the exemplary term “below” can encompass both an orientation ofabove and below. The apparatus may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein may likewise be interpreted accordingly.

Some embodiments of the disclosure will now be described with referenceto the drawings, wherein like reference numerals are generally used torefer to like elements throughout. In the following description, forpurposes of explanation, numerous specific details are set forth inorder to provide a thorough understanding of the claimed subject matter.It is evident, however, that the claimed subject matter may be practicedwithout these specific details. In other instances, structures anddevices are illustrated in block diagram form in order to facilitatedescribing the claimed subject matter.

Additional operations can be provided before, during, and/or after thestages described in these embodiments. Some of the stages that aredescribed can be replaced or eliminated for different embodiments.Additional features can be added to the semiconductor device structure.Some of the features described below can be replaced or eliminated fordifferent embodiments. Although some embodiments are discussed withoperations performed in a particular order, these operations may beperformed in another logical order.

As used herein, a “layer” is a region, such as an area comprisingarbitrary boundaries, and does not necessarily comprise a uniformthickness. For example, a layer can be a region comprising at least somevariation in thickness.

During a BEOL fabrication process, various dielectric layers andinterconnect structures are formed overlying a semiconductor substratethat was fabricated during a FEOL fabrication process. With many modernBEOL fabrication processes, there is a need to form interconnectstructures having very small critical dimensions so that they can beelectrically connected to various device elements that were formed inand/or on the semiconductor substrate during a FEOL fabrication process.During the BEOL fabrication process, various etching steps areperformed, and in some cases, due to the small critical dimensionsinvolved, an under etching problem can occur during the process offorming via openings in which conductive vias are ultimately formed. Itwould be desirable to reduce or eliminate such under etching problemswithout making the fabrication sequence used to form the via openingsunnecessarily complex.

To address these issues, fabrication techniques are provided thatutilize a hard mask that comprises a tungsten-based material whenforming via openings during a BEOL fabrication process. When a hard maskthat comprises a tungsten-based material is used during the process offorming the via openings, etching by-products (e.g., tungsten fluoride(WF_(x))) are produced that have a lower boiling point, andunder-etching effects can be reduced. Due to the lower boiling pointetching by-products do not tend to accumulate in and block etching ofthe via openings that are being etched. As a result, under etching ofthe via openings can be greatly reduced or eliminated. In somenon-limiting embodiments, the disclosed techniques can be used tofabricate vias for interconnect structures having small criticaldimensions, such as those in a metal one (M1) interconnect layer thatare used to provide a connection to conductive features that part of ametal zero (M0) layer (e.g., that are used to provide an electricalconnection to device elements formed in a semiconductor substrate thatwas fabricated during a FEOL fabrication process).

FIG. 1 is a flowchart of a method 10 of forming an interconnectstructure of a semiconductor device structure in accordance with someembodiments. It is understood that additional steps can be providedbefore, during, and after the method 10, and some of the steps describedcan be replaced or eliminated for other embodiments of the method 10.

The method 10 begins at step 12 in which a semiconductor structure canbe provided, created, fabricated, or otherwise formed. One non-limitingexample of such a semiconductor structure is described below withreference to FIG. 2A. The semiconductor structure has one or moreconductive features formed therein. The semiconductor structure can varydepending on the implementation. The semiconductor structure can includeany number of materials layers formed over a semiconductor substrate.The semiconductor substrate can include any number of conductivefeatures and device elements formed in and/or over the semiconductorsubstrate. Conductive features can include, for example, plugs,interconnects, wiring lines, etc. Device elements can include, forexample, transistors, diodes, capacitors, etc. For example, thetransistors may be metal oxide semiconductor field effect transistors(MOSFETs), complementary metal oxide semiconductor (CMOS) transistors,bipolar junction transistors (BJT), high-voltage transistors,high-frequency transistors, p-channel field effect transistors (PFETs)and/or n channel field effect transistors (NFETs), etc. In someembodiments, the transistors may be planar FETs, multi-gate FET devices,FinFET devices, gate-all-around (GAA) FET device (also referred to assurround-gate FET devices), and/or Nanosheet FET devices, as will bedescribed in greater detail below.

At step 14, a first etch stop layer is formed overlying thesemiconductor structure. The method 10 continues with step 16 in which asecond etch stop layer is formed overlying the first etch stop layer.The method 10 continues with step 18 in which a dielectric layer isformed overlying the second etch stop layer.

At steps 20 through 34 the interconnect structure is formed in thedielectric layer. The method 10 continues with step 20 in which a hardmask is formed overlying the dielectric layer. The hard mask comprises atungsten-based material, such as, tungsten carbide (WC) or tungstennitride (WN). The method 10 continues with step 22 in which a trench ispatterned in the hard mask to create a patterned hard mask.

The method 10 continues with step 24 in which a multi-layer resist layeris formed over the patterned hard mask. The multi-layer resist layercomprises an upper layer, a middle layer, and a bottom layer. The method10 continues with step 26 in which a first set of etching processes isperformed to pattern the multi-layer resist layer. This forms apatterned bottom layer. The method 10 continues with step 28 in whichanother etching process is performed, using the patterned bottom layeras a mask, to form a via opening that extends partially through thedielectric layer.

The method 10 continues with step 30 in which a dry etching process isperformed, using the patterned hard mask as an etch mask, to extend thetrench further into the dielectric layer and to extend the via openingthrough the second etch stop layer. The method 10 continues with step 32in which a wet etching process is performed to extend the via openingthrough the first etch stop layer to reach the conductive feature. Themethod 10 continues with step 34 in which the via opening and the trenchare filled with a conductive material to form the interconnect structurein the dielectric layer. The interconnect structure electricallycontacts one or more of the conductive features.

In accordance with the method 10, using a hard mask that comprises atungsten-based material can be advantageous in comparison to using otherconventional types of hard masks, such as, metal nitride hard masks. Onereason is because the etching by-products, that are generated duringvarious etching steps, do not tend to block via openings that are beingetched, and therefore, under-etching can be reduced. To explain further,when the trench is patterned in the hard mask (at step 22), or when thepatterned hard mask is used as an etch mask during the dry etchingprocess (at step 30), etching by-products are produced that have arelatively low boiling point (e.g., relatively high volatility ortendency to vaporize) in comparison to the by-products that are producedwhen the hard mask material is made of other types of materials that areoften used as hard mask layer, such as metal nitrides like TiN. Toexplain further, when etching a dielectric material, a fluoro-containingetching gas (e.g., CF₄, C₄F₈, etc.) is usually applied. Reactionsbetween this etching gas and the hard mask material can result influorinated etching by-products being generated. Depending on thematerial used for the hard mask, different fluorinated etchingby-products can result that have a range of different boiling points(e.g., some etching by products are less volatile while others are morevolatile.

For example, when a TiN hardmask is used, a titanium fluoride (TiF_(x))by-product is generated. The titanium fluoride (TiF_(x)) by-product ismetallic and has relatively high boiling point (e.g., has less tendencyto vaporize and is less volatile). The titanium fluoride (TiF_(x))by-product can accumulate in and block the via openings, which in turn,can result in under-etching of the via openings. This is especially truewhen the via openings are for vias having small critical dimensions. Ascritical dimensions of the via become smaller, these titanium fluoride(TiF_(x)) by-products can negatively impact (e.g., block or prevent)etching of the via openings. As a result of this blockage, under-etchingof the via openings can occur. For example, it has been observed thatwhen other types of hard masks are utilized, such as metal nitride hardmasks (e.g., a titanium nitride (TiN) hard mask or the like),under-etching of via openings occurs.

These etching by-products can be deposited and accumulate in the smalland narrow via openings and/or along the trench, which can later causeunder etching problems to occur during subsequent etching steps duringthe process of forming the via openings. If under etching is leftunaddressed, the vias that are eventually formed in the under etched viaopenings have degraded electrical contact with the conductive featurethat they contact. For example, in some cases, this can result in a viathat exhibits poor quality of contact with the conductive feature (e.g.,a via that has poor performance). In an extreme case, this can result ina via that does not contact the conductive feature at all (e.g., a viathat is inoperable). In either case, if under etching is not addressed,the quality of the via is negatively impacted.

By contrast, when a hard mask that comprises a tungsten-based materialis used (as in method 10), under-etching issues can be reduced incomparison to other approaches that use different hard mask materials.When a hard mask that comprises a tungsten-based material is used, theetching by-products have a lower boiling point, and under-etchingeffects can be reduced. To explain further, when a hard mask thatcomprises a tungsten-based material is used, tungsten fluoride (WF_(x))etching by-products are produced that have a lower boiling point thanthe etching by-products that result when another material, like titaniumnitride (TiN), is used as the hard mask. Due to the lower boiling pointof tungsten fluoride, etching by-products do not tend to accumulate inthe via openings. As a result, under etching of the via openings can begreatly reduced or eliminated.

One option for addressing under etching would be to perform additionaletching steps, but this would require additional complexity to thefabrication sequence in order to extend via opening to reach theconductive feature. In addition, additional etch stop layers would berequired, which would add even more complexity to the overallfabrication sequence. As such, another advantage of method 10 is thatbecause under etching is no longer a concern, the number of etchingsteps that are needed can be reduced. To explain further, in method 10,once the initial via opening is formed (at step 28), only two etchingsteps 30, 32 (e.g., a dry etch step at 30 followed by a wet etch step at32) are performed to extend the via opening to reach the conductivefeature. As such, the number of etch stop layers that are needed inmethod 10 can be reduced in comparison to other approaches where underetching is a concern, which can further simplify the over fabricationsequence used to form the interconnect.

The discussion that follows illustrates embodiments of an interconnectstructure 195 of a semiconductor device structure that can be fabricatedin accordance with the method 10 of FIG. 1 .

FIGS. 2A-2N are cross-sectional views of various stages of a process forforming an interconnect structure 195 of a semiconductor devicestructure 100 in accordance with some embodiments. FIG. 2A illustrates asemiconductor structure 120 of the semiconductor device structure 100 inaccordance with some embodiments. An interconnect structure (not shownin FIG. 2A) may be provided within the semiconductor structure 120.FIGS. 2B-2N show various processing steps involved in a method forfabricating the interconnect structure within a material layer 103 ofthe semiconductor structure 120. The interconnect structure 195 isillustrated in FIG. 2N.

As shown in FIG. 2A, in accordance with some embodiments, thesemiconductor structure 120 may include front-end-of-line (FEOL)structures and back-end-of-line (BEOL) structures. In accordance withsome non-limiting embodiments, the FEOL structures can include asemiconductor substrate 101, and the BEOL structure can include firstmaterial layers 102 and second material layers 103. The first materiallayers 102 have a number of conductive features 108 formed therein. Thesecond material layers 103 are layers in which an interconnect structure(not shown) will be fabricated as part of an integrated circuitfabrication process. As shown in FIG. 2N, vias of the interconnectstructure 195 may contact one or more of the conductive features 108. Insome non-limiting embodiments, the interconnect structure has a dualdamascene architecture, but it should be appreciated that the disclosedembodiments can also be used to provide other alternative interconnectstructures including, but not limited to, interconnect structures havinga single damascene architecture. In some non-limiting embodiments, thefirst material layers 102 and the conductive features 108 formed thereinthat may be part of metal zero (M0) interconnect layer of a BEOLarchitecture, and the second material layers 103 and the interconnectstructure that will be formed therein can be part of metal one (M1)interconnect layer of a BEOL architecture. However, it should beappreciated that in other embodiments, the first material layers 102 andthe second material layers 103 can be implemented at other metal layersof a BEOL architecture.

Although not illustrated in FIG. 2A, it should be noted that thesemiconductor substrate 101 may include various features that are notillustrated for sake of clarity and simplicity. In this regard, thesemiconductor substrate 101 may include one or more dielectric layershaving multiple conductive features formed therein that are electricallyconnected to device elements formed in the semiconductor substrate 101.The dielectric layer covers device elements formed in and/or over thesemiconductor substrate 101. In some embodiments, the conductivefeatures can be made of or include copper (Cu), aluminum (Al), tungsten(W), titanium (Ti), cobalt (Co), nickel (Ni), gold (Au), platinum (Pt),one or more other suitable materials, or a combination thereof. Variousprocesses, including deposition, etching, planarization, or the like,may be used to form the conductive features (not shown) in thedielectric layer of the semiconductor substrate 101.

In some embodiments, the semiconductor substrate 101 is a bulksemiconductor substrate, such as a semiconductor wafer. For example, thesemiconductor substrate is a silicon wafer. The semiconductor substrateincludes silicon or another elementary semiconductor material such asgermanium. In some other embodiments, the semiconductor substrateincludes a compound semiconductor. The compound semiconductor includesgallium arsenide, silicon carbide, indium arsenide, indium phosphide,another suitable material, or a combination thereof. In someembodiments, the semiconductor substrate 101 is asemiconductor-on-insulator (SOI) substrate. The SOI substrate may befabricated by using a separation by implantation of oxygen (SIMOX)process, a wafer bonding process, another applicable method, or acombination thereof.

In some embodiments, parts of or all of the semiconductor substrate 101in FIG. 2A are fabricated by a semiconductor manufacturing process flowsuch as a complementary metal-oxide-semiconductor (CMOS) technologyprocess flow, and thus some processes are only briefly described herein.Furthermore, the semiconductor substrate 101 includes various devicesand features, such as additional transistors, bipolar junctiontransistors, resistors, capacitors, diodes, and fuses, but is simplifiedfor a better understanding of the embodiments of the present disclosure.

In some embodiments, the semiconductor substrate 101 in FIG. 2A is anintermediate structure fabricated during manufacturing of an integratedcircuit, or a portion thereof. In some embodiments, various deviceelements are formed in and/or over the semiconductor substrate 101. Thedevice elements are not shown in figures for the purpose of simplicityand clarity. Examples of the various device elements includetransistors, diodes, another suitable element, or a combination thereof.For example, the transistors may be metal oxide semiconductor fieldeffect transistors (MOSFET), complementary metal oxide semiconductor(CMOS) transistors, bipolar junction transistors (BJT), high-voltagetransistors, high-frequency transistors, p-channel field effecttransistors (PFETs) and/or n channel field effect transistors (NFETs),etc. In some embodiments, the transistors may be planar FETs, multi-gateFET devices, FinFET devices, gate-all-around (GAA) FET device (alsoreferred to as surround-gate FET devices), and/or Nanosheet FET devices.Multi-gate FET devices include those transistors whose gate structuresare formed on at least two-sides of a channel region. These multi-gatedevices may include a p-type metal-oxide-semiconductor device or ann-type metal-oxide-semiconductor multi-gate device. Examples ofmulti-gate FET devices can include, for example, double-gate FETdevices, triple-gate FET devices, omega-gate FET devices. A FinFETdevice is a field effect transistor with fin-like channels. A GAA FETdevice includes any device that has its gate structure, or portionthereof, formed on 4-sides of a channel region (e.g., surrounding aportion of a channel region). A nanosheet FET device includes any devicethat has channel regions in the form of nanosheets, where the term“nanosheet” designates any material portion with nanoscale, or evenmicroscale dimensions, and having an elongate shape, regardless of thecross-sectional shape of this portion. Thus, this term designates bothcircular and substantially circular cross-section elongate materialportions, e.g., nanowires, and beam or bar-shaped material portionsincluding for example a cylindrical or substantially rectangularcross-section.

Various processes, such as front-end-of-line (FEOL) semiconductorfabrication processes, are performed to form the various deviceelements. The FEOL semiconductor fabrication processes may includedeposition, etching, implantation, photolithography, annealing,planarization, one or more other applicable processes, or a combinationthereof.

In some embodiments, the semiconductor substrate is an un-dopedsubstrate. However, in some other embodiments, the semiconductorsubstrate is a doped substrate such as a P-type substrate or an N-typesubstrate. In some embodiments, the semiconductor substrate includesvarious doped regions (not shown) depending on the design requirementsof the semiconductor device. The doped regions include, for example,p-type wells and/or n-type wells. In some embodiments, the doped regionsare doped with p-type dopants. For example, the doped regions are dopedwith boron or BF₂. In some embodiments, the doped regions are doped withn-type dopants. For example, the doped regions are doped with phosphoror arsenic. In some embodiments, some of the doped regions are p-typedoped, and the other doped regions are n-type doped.

In some embodiments, isolation features (not shown) are formed in thesemiconductor substrate 101. The isolation features are used to defineactive regions and electrically isolate various device elements formedin and/or over the semiconductor substrate 101 in the active regions. Insome embodiments, the isolation features include shallow trenchisolation (STI) features, local oxidation of silicon (LOCOS) features,other suitable isolation features, or a combination thereof.

Material layer 102 includes an etch stop layer 104 and a dielectriclayer 106 having a number of conductive features 108. It should beappreciated that the material layer 102 in accordance with embodimentsof the present disclosure is not limited to these layers and conductivefeatures, but rather, that the layers and conductive features are shownto illustrate one non-limiting embodiment. For example, the materiallayer 102 may include more or less layers. For instance, in some otherembodiments, the material layer 102 includes one or more additionallayers positioned between the etch stop layer 104 and the substrate 101.In some other embodiments, the material layer 102 includes one or moreadditional layers positioned between the etch stop layer 112 and thedielectric layer 106. In some other embodiments, the material layer 102includes one or more additional layers positioned above dielectric layer106 and the conductive features 108 formed therein (e.g., one or moreadditional layers positioned under the etch stop layer 110). In someother embodiments, the material layer 102 merely includes the etch stoplayer 104 and/or the dielectric layer 106.

As shown in FIG. 2A, material layer 102 can include an etch stop layer104 that is formed over the semiconductor substrate 101 along with adielectric layer 106 is deposited over the etch stop layer 104.Embodiments of the etch stop layer 104 will be described below withreference to first etch stop layer 110. The dielectric layer 106 mayserve as an ILD or IMD layer of an interconnection structure. AlthoughFIG. 2A shows that the dielectric layer 106 is a single layer,embodiments of the disclosure are not limited thereto. In some otherembodiments, the dielectric layer 106 is a multi-layer structureincluding dielectric sub-layers (not shown).

In some embodiments, the dielectric layer 106 is made of or includes alow dielectric constant (low-k) material, an extreme low-k (ELK)material, silicon oxide, silicon oxynitride, borosilicate glass (BSG),phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG),fluorinated silicate glass (FSG), a porous dielectric material, one ormore other suitable materials, or a combination thereof. In someembodiments, the dielectric layer 106 includes a low-k dielectricmaterial or ELK material. The low-k or ELK material may have adielectric constant that is less than that of standard silicon dioxide.For example, the low-k material may have a dielectric constant in arange from about 1.5 to about 3.5. The ELK material may have adielectric constant, which is less than about 2.5 or in a range fromabout 1.5 to about 2.5. Using a low-k or ELK material as the dielectriclayer 106 is helpful for reducing resistance capacitance (RC) delaytime. A wide variety of low-k or ELK materials may be used for formingthe dielectric layer 106. In some embodiments, the low-k dielectricmaterial includes fluorine-doped silicon dioxide, carbon-doped silicondioxide, porous silicon dioxide, porous carbon-doped silicon dioxide,spin-on organic polymeric dielectric, spin-on silicone based polymericdielectric, polyimides, aromatic polymers, fluorine-doped amorphouscarbon, vapor-deposited parylene, another suitable material, or acombination thereof.

In some embodiments, the dielectric layer 106 is deposited using achemical vapor deposition (CVD) process, an atomic layer deposition(ALD) process, a spin-on process, a spray coating process, one or moreother applicable processes, or a combination thereof.

Although not illustrated in FIG. 2A, in some embodiments, ananti-reflective coating layer may be deposited over the dielectric layer114. The anti-reflective coating layer may be made of siliconoxycarbide, another suitable material, or a combination thereof. In someembodiments, the anti-reflective coating layer is a nitrogen-freeanti-reflective coating (NFARC) layer.

Multiple conductive features 108 may be formed in the dielectric layer106. The conductive features 108 may be conductive lines or othersuitable conductive features. At least some of the conductive features108 may be electrically connected to device elements within thesemiconductor substrate 101. For example, the conductive features 108may be electrically connected to the device elements through theconductive features (not shown) in the dielectric layer of thesemiconductor substrate 101.

Although FIG. 2A shows that each of the conductive features 108 is asingle layer, embodiments of the disclosure are not limited thereto.Although not shown, depending on the embodiment, the conductive features108 may be single or dual damascene structures. In some embodiments, theconductive features are made of or include copper (Cu), aluminum (Al),tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), gold (Au),platinum (Pt), one or more other suitable materials, or a combinationthereof. The conductive features 108 may be a multi-layer structureincluding conductive sub-layers. For example, the conductive sub-layersinclude a diffusion barrier layer, a seed layer, a metal-filling layer,one or more other suitable layers, or a combination thereof. Theconductive sub-layers are not shown in figures for the purpose ofsimplicity and clarity. Various processes, including deposition,etching, planarization, or the like, may be used to form the conductivefeatures 108 in the dielectric layer 106.

Conductive features 108 are shown in FIG. 2A as an example. It should benoted that the dimensions of the conductive features 108 shown in FIG.2A are only an example and not a limitation to the disclosure, and aswill be described below, the conductive features 108 have criticaldimensions (CDs) that are substantially smaller than the dimensions ofconductive features that are provided in layers at or above theconductive features 108. It should be appreciated that the conductivefeatures 108 shown in FIGS. 2A-2N are not drawn to scale and havecritical dimensions that are relatively small in comparison. Forexample, the width (W1) of conductive feature 108 as shown in FIG. 2Ecan be substantially smaller in comparison to other features such asmask opening 147-1 of FIG. 2E. For instance, in one non-limitingexample, the first mask openings 147-1, 147-2 illustrated in FIG. 2E canhave widths (W2, W3) that range from about 25 to 30 nanometers and arethus substantially larger than the width (W1) of conductive feature 108which can have a width that can range from about 5 to 20 nanometers(e.g., between 8 and 13 nanometers). The importance of this differencein dimensions between conductive features 108 and other features will bedescribed in detail below.

As shown in FIGS. 2A, various material layers 103 are formed overmaterial layers 102 in accordance with some embodiments. In particular,FIG. 2A illustrates an embodiment where the material layer 103 includesa first etch stop layer 110 formed over the dielectric layer 106, asecond etch stop layer 112 formed over the first etch stop layer 110 anda dielectric layer 106 formed over the second etch stop layer 112. Itshould be appreciated that the material layer 103 in accordance withembodiments of the present disclosure is not limited to these layers,but rather, that the layers are shown to illustrate one non-limitingembodiment. For example, the material layer 103 may include more or lesslayers. For instance, in some other embodiments, the material layer 103includes one or more additional layers positioned between the etch stoplayer 110, the second etch stop layer 112, and the dielectric layer 114.In some other embodiments, the material layer 103 includes one or moreadditional layers positioned over the dielectric layer 114. In someother embodiments, the material layer 103 includes one or moreadditional layers positioned under the etch stop layer 110. In someother embodiments, the material layer 103 merely includes the etch stoplayer 110 and the dielectric layer 114.

As shown in FIG. 2A, the first etch stop layer 110 may be formed overthe dielectric layer 106, and a second etch stop layer 112 may be formedover the first etch stop layer 110. Depending on the implementation, thefirst and second etch stop layers 110, 112 may be formed from more thanone layer. The first and second etch stop layers 110, 112 cover theconductive features 108 to protect the conductive features 108 frombeing damaged during subsequent etching processes. The first and secondetch stop layers 110, 112 may serve as barrier layers that protect thedielectric layer 106 from diffusion of a metal material from subsequentconductive features during subsequent thermal processes or cycles.

In some embodiments, the thickness of the etch stop layer(s) can be in arange from about 10 Å to about 100 Å. In some embodiments, each of theetch stop layers can be made of or include plasma-enhanced oxide (PEOX),tetraethoxysilane (TEOS), aluminum nitride (AlN), aluminum oxide(AlO_(x)), silicon carbide (SiC), silicon carbonitride (SiCN), siliconoxycarbide (SiCO), silicon nitride (SiN), silicon oxynitride (SiON), oneor more other suitable materials, or a combination thereof. Examples ofSiC include oxygen-doped silicon carbide (SiC:O, also known as ODC) andnitrogen-doped silicon carbide (SiC:N, also known as NDC). For instance,in one non-limiting embodiment, the first etch stop layer 110 may bemade of or include a layer of aluminum oxide (AlO_(x)), and the secondetch stop layer 112 may be made of or include a layer of silicon oxide,silicon carbide (SiC), silicon oxycarbide (SiOC), a siliconoxycarbonitride (SiOCN), another suitable material, or a combinationthereof.

In some embodiments, the etch stop layers 110, 112 can be formed bychemical vapor deposition (CVD), spin-on coating, another applicableprocess, or a combination thereof. The CVD process may include, but isnot limited to, a low pressure CVD (LPCVD) process, a low-temperatureCVD (LTCVD) process, a rapid thermal CVS (RTCVD) process, a plasmaenhanced CVD (PECVD) process, a high density plasma CVD (HDPCVD)process, an atomic layer deposition (ALD) process, a plasma enhancedatomic layer deposition (PEALD) process, another applicable process, ora combination thereof.

As shown in FIG. 2A, in accordance with some embodiments, a dielectriclayer 114 is deposited over the second etch stop layer 112. Thedielectric layer 114 serves as an IMD layer of an interconnectionstructure. In some embodiments, the dielectric layer 114 is thicker thanthe dielectric layer 106, but embodiments of the disclosure are notlimited thereto. For instance, in some embodiments, the thickness of thedielectric layer 106 is in a range from about 100 Å to about 300 Å,whereas the thickness of the dielectric layer 114 is in a range fromabout 200 Å to about 400 Å. Although FIG. 2A shows that the dielectriclayer 114 as a single layer, embodiments of the disclosure are notlimited thereto. In some other embodiments, the dielectric layer 114 isa multi-layer structure including dielectric sub-layers (not shown). Thematerials and/or formation methods of the dielectric layer 114 are thesame as or similar to those of the dielectric layer 106, as illustratedin the aforementioned embodiments, and therefore are not repeated.

As shown in FIG. 2B, a hard mask 130 can then be formed over thedielectric layer 114. The hard mask 130 can include one or more layersof material. In accordance with the disclosed embodiments, the hard mask130 includes at least one hard mask layer 134 comprised of a tungstencontaining material or tungsten-based material, such as a tungstencarbide (WC_(x)) layer or a tungsten nitride (WN_(x)) layer. In moregeneral terms, the hard mask layer 134 can be made of or includematerials that when etched with an etchant gas result in relatively lowboiling point etching by-products in comparison to other types ofmaterials that are often used as hard mask layer, such as metal nitridesthat may include, but are not limited to, titanium nitride, etc.

In the non-limiting example illustrated in FIG. 2B, the hard mask 130 isa mask stack that includes a first oxide layer 132 formed over thedielectric layer 114, the hard mask layer 134 formed over the firstoxide layer 132, and a second oxide layer 136 formed over the hard masklayer 134. In some embodiments, the first oxide layer 132 can functionas an anti-reflective coating layer.

The first oxide layer 132 can protect a dielectric layer 114 fromdiffusion of metal material during subsequent thermal processes orcycles. The hard mask layer 134 may then be deposited over the firstoxide layer 132, and the second oxide layer 136 may then be depositedover the hard mask layer 134 to result in a structure or stack in whichthe hard mask layer 134 is longitudinally sandwiched between the oxidelayers 132, 136.

In some non-limiting embodiments, the first oxide layer 132 and thesecond oxide layer 136 can be made of or include an oxide layer, siliconcarbide (SiC) layer, silicon oxycarbide (SiOC) layer, silicon nitride(SiN) layer, one or more other suitable materials, or a combinationthereof. In some embodiments, the first oxide layer 132 and the secondoxide layer 136 can be deposited using a PVD process, a CVD process, anALD process, one or more other applicable processes, or a combinationthereof. In some embodiments, the second oxide layer 136 may have athickness that is greater than the first oxide layer 132.

In some embodiments, the hard mask layer 134 is made of or includes atungsten-based material. In some embodiments, the hard mask layer 134may be made of or include a tungsten-based layer such as a tungsten (W)layer, a tungsten carbide (WC_(x)) layer, a tungsten nitride (WN_(x))layer, a tungsten boride (WB) layer, a tungsten boron carbide (WBC)layer, a tungsten boron nitride (WBN) layer, a tungsten carbonitride(WCN) layer, or any combination thereof. Tungsten carbide (WC_(x))films, for example, can provide characteristics such as strong adhesion,stress and a high etch selectivity when implemented as a hard mask. Insome embodiments, the hard mask layer 134 may be made of or include atantalum nitride (TaN) layer, a molybdenum carbide (MoC) layer, or aZirconium (Zr) layer, or any combination thereof. Although the hard masklayer 134 is illustrated as a single layer in FIG. 2B, in otherembodiments, the hard mask layer 134 can be a multi-layer structure thatincludes multiple layers of materials in addition to a tungsten-basedmaterial as described above. The hard mask layer 134 can be formed byusing an applicable deposition process, such as a PVD process, a platingprocess, a CVD process, a spin-on process, one or more other applicableprocesses, or a combination thereof.

As shown in FIG. 2C, steps are performed to form a first trench 138 inthe hard mask 130. Although not illustrated in FIG. 2C, a photoresistlayer (or other photo-sensitive layer capable of being patterned using aphotolithography process) can be formed in and overlying the hard mask130. Depending on the implementation, the photoresist layer can be asingle layer of material, or a multi-layer structure including multiplesub-layers. The photoresist layer may be negative type or positive type.Although not shown in FIG. 2C, the photoresist layer can be patterned toform a patterned photoresist layer over the hard mask 130. The patternedphotoresist layer defines a trench pattern that can be transferred intoa portion of the hard mask 130. One or more etching processes can thenbe sequentially performed to remove exposed portions of the second oxidelayer 136, the hard mask layer 134, and the first oxide layer 132, and,as shown in FIG. 2C, leave portions of the second oxide layer 136-1, thehard mask layer 134-1, and the first oxide layer 132-1 remaining todefine the trench 138 in the hard mask 130. The hard mask layer 134etches with a high selectivity with respect to the first and secondoxide layers 132, 136.

After etching the first trench 138, a removal process can then beperformed to remove the patterned photoresist layer (not illustrated) sothat the patterned hard mask 130-1 remains over the dielectric layer 114with the first trench 138 formed therein. As a result of the etchingprocesses that are applied, the pattern of trench pattern 138 istransferred to the patterned hard mask 130-1. After processing in FIG.2C is complete, portions of the patterned hard mask 130-1 that remain(e.g., the remaining portions of the second oxide layer 136-1, the hardmask layer 134-1, and the first oxide layer 132-1) form are maskelements that collectively define a first trench 138 having a pattern orprofile that will subsequently be transferred into the dielectric layer114.

As shown in FIG. 2D, a multi-layer resist layer 140 can then be formedin and over the patterned hard mask 130-1. The use of a multi-layerresist scheme can allow for via openings to be patterned that have largeaspect ratio, while also providing improvements in line edge roughness(LER) and line width roughness (LWR), among other benefits. As shown inFIG. 2D, the multi-layer resist layer 140 has a multi-layer structurethat includes multiple layers 142, 144, 146. In non-limiting embodimentshown in FIG. 2D, the multi-layer resist layer 140 is a tri-layerstructure including a bottom layer 142 formed over the patterned hardmask 130-1, a middle layer 144 formed over the bottom layer 142, and anupper layer 146 formed over the middle layer 144. Although FIG. 2D showsthat the multi-layer resist layer 140 includes three layers, it shouldbe appreciated that embodiments of the disclosure are not limitedthereto, and that in other embodiments, the multi-layer resist layer 140can include fewer or more layers. As such, it is understood that inother embodiments, one or more layers of the tri-layer photoresist maybe omitted, or additional layers may be provided as a part of thetri-layer photoresist, and the layers may be formed in differencesequences.

As will be explained in greater detail below, in some embodiments, thebottom layer 142 and the upper layer 146 are organic layers (e.g., madeof or including an organic material), and the middle layer 144 is asilicon-containing layer. For instance, in some embodiments, the bottomlayer 142 includes a C_(x)H_(y)O_(z) material, the middle layer 144includes a SiC_(x)H_(y)O_(z) material, and the upper layer 146 includesa C_(x)H_(y)O_(z) material. The C_(x)H_(y)O_(z) material of the bottomlayer 142 may be identical to the C_(x)H_(y)O_(z) material of the upperlayer 146 in some embodiments, but they may also be different materialsin other embodiments. The upper layer 146 may be a photo-sensitive layer(e.g., photoresist) capable of being patterned using a photolithographyprocess. For example, the upper layer 146 also includes aphoto-sensitive element, such as a photo-acid generator (PAG) thatallows a photolithography process to be performed to pattern the upperlayer 146. The upper layer 146 may be negative type or positive type.

As shown in FIG. 2D, the bottom layer 142 is deposited in and overlyingthe patterned hard mask 130-1 to fill the first trench 138 that isformed in the patterned hard mask 130-1. In some embodiments, the bottomlayer 142 is an organic layer and is made of organic material. In someembodiments, the bottom layer 142 layer contains a material that ispatternable. In some embodiments, the bottom layer 142 layer has acomposition tuned to provide anti-reflection properties. In someembodiments, the bottom layer 142 includes photo-acid generator (PAG),thermal-acid generator (TAG), photo-base generator (PBG), thermal-basegenerator (TBG), and/or quencher. In some embodiments, the bottom layer142 is deposited by a spin coating process. In some other embodiments,the bottom layer 142 is deposited by another applicable depositionprocess.

As shown in FIG. 2D, the middle layer 144 is deposited over the bottomlayer 142, in accordance with some embodiments. In some embodiments, themiddle layer 144 includes a silicon-containing layer (e.g., silicon hardmask material). In some embodiments, the middle layer 144 includes asilicon-containing inorganic polymer. In some embodiments, the middlelayer 144 includes a siloxane polymer (e.g., a polymer having a backboneof O—Si—O—Si— etc.). The silicon ratio of the middle layer 144 materialmay be adjusted to control the etch rate. In some other embodiments themiddle layer 144 includes silicon oxide (e.g., spin-on glass (SOG)),silicon nitride, silicon oxynitride, polycrystalline silicon, ametal-containing organic polymer material that contains metal such astitanium, titanium nitride, aluminum, and/or tantalum; and/or othersuitable materials. In some embodiments, the middle layer 144 includesphoto-acid generator (PAG), thermal-acid generator (TAG), photo-basegenerator (PBG), thermal-base generator (TBG), and/or quencher. In someembodiments, the middle layer 144 is deposited by a spin coatingprocess. In some other embodiments, the middle layer 144 is deposited byanother applicable deposition process.

As shown in FIG. 2D, the upper layer 146 is deposited over the middlelayer 144, in accordance with some embodiments. In some embodiments, theupper layer 146 is a third, and top, layer of the multi-layer resistlayer 140. In some embodiments, the upper layer 146 is an organic layer,a photoresist (PR) layer or a photosensitive layer, which is operable tobe patterned by radiation. In some embodiments, the material of theupper layer 146 is the same as the material of the bottom layer 142. Insome other embodiments, the material of the upper layer 146 is differentfrom the material of the bottom layer 142. For instance, in someembodiments, the upper layer 146 is made of or includes polyimide,metal-containing organic-inorganic hybrid compound, one or more othersuitable materials, or a combination thereof. Examples of themetal-containing organic-inorganic hybrid compound may includemetal-containing oxide (such as ZrO_(x) or TiO_(x)) or anotherorganic-inorganic hybrid compound.

In some embodiments, the chemical properties of the portion of the upperlayer 146 struck by incident radiation changes in a manner that dependson the type of photoresist used. In some embodiments, the upper layer146 is a suitable positive tone resist. Positive tone resist refers to aphotoresist material that when exposed to radiation (typically UV light)becomes insoluble to a negative tone developer, while the portion of thephotoresist that is not exposed (or exposed less) is soluble in thenegative tone developer. In some embodiments, the term “negative tonedeveloper” refers to any suitable developer that selectively dissolvesand removes areas that received no exposure dose or an exposure dosebelow a predetermined threshold exposure dose value. In someembodiments, the negative tone developer includes an organic solvent(e.g., a ketone-based solvent, ester-based solvent, alcohol-basedsolvent, amide-based solvent, ether-based solvent, hydrocarbon-basedsolvent, and/or other suitable solvent).

In some embodiments, the upper layer 146 includes a carbon backbonepolymer. In some embodiments, the upper layer 146 includes othersuitable components such as a solvent and/or photo acid generators. Insome embodiments, the upper layer 146 is a chemical amplified (CA)resist. In some embodiments, the photoresist layer includes a photo-acidgenerator (PAG) distributed in the photoresist layer. In someembodiments, when absorbing photo energy from an exposure process, thePAG forms a small amount of acid. In some embodiments, the resistincludes a polymer material that varies its solubility to a developerwhen the polymer is reacted with this generated acid. In someembodiments, the chemical amplified resist is a positive tone resist.

In some embodiments, the upper layer 146 is deposited by a spin coatingprocess. In some other embodiments, the upper layer 146 is deposited byanother applicable deposition process.

In some embodiments, the thicknesses of the bottom layer 142, the middlelayer 144 and the upper layer 146 are different from each other. In someembodiments, the thickness of the bottom layer 142 is in a range fromabout 200 nm to about 400 nm. In some embodiments, the thickness of themiddle layer 144 is in a range from about 20 nm to about 40 nm. In someembodiments, the thickness of the upper layer 146 is in a range fromabout 80 nm to about 200 nm.

As shown in FIG. 2E, the upper layer 146 is developed and can bepatterned to form a patterned upper layer 146-1 (or photoresist mask)with one or more first mask openings 147-1, 147-2. In some embodiments,the upper layer 146 is exposed to a radiation beam. In some embodiments,the radiation beam exposes the upper layer 146 using a lithographysystem that provides a pattern of the radiation according to an ICdesign layout. In some embodiments, a lithography system employs anextreme ultraviolet (EUV) photolithography process to expose the upperlayer 146 to extreme ultraviolet (EUV) radiation. The EUVphotolithography process, may include one or more exposures, as well asdeveloping, rinsing, and baking processes (not necessarily performed inthis order).

For example, after the exposed upper layer 146 is exposed, a developeris applied to the exposed upper layer 146 to form the patterned upperlayer 146-1. In some embodiments, a negative tone developer is appliedto the exposed upper layer 146. The term “negative tone developer”refers to a developer that selectively dissolves and removes areas thatreceived no exposure dose or an exposure dose below a predeterminedthreshold exposure dose value. In some embodiments, the developerincludes an organic solvent or a mixture of organic solvents, such asmethyl a-amyl ketone (MAK) or a mixture involving the MAK. In some otherembodiments, a developer includes a water based developer, such astetramethylammonium hydroxide (TMAH). In some embodiments, applying adeveloper includes spraying a developer on the exposed resist film, forexample by a spin-on process. In some embodiments, the developer removesthe non-exposed regions of the resist leaving the portions that havebeen exposed. In some embodiments, after development, one or moreadditional etching processes may be performed.

To simplify the drawings, only two first mask openings 147-1, 147-2 aredepicted in the patterned upper layer 146-1. The first mask openings147-1, 147-2 expose portions of the underlying middle layer 144. Theregion of the patterned upper layer 146-1 that is between the first maskopenings 147-1, 147-2 serves as an isolation feature. The first maskopenings 147-1, 147-2 that are defined in the patterned upper layer146-1 are eventually used define a pattern for second mask openings148-1, 148-2 that will subsequently be formed in and through the middlelayer 144 and the bottom layer 142. As mentioned above, due to thenature of the EUV lithography process used to pattern the upper layer146, the first mask openings 147-1, 147-2 are formed in the patternedupper layer 146-1 can have different dimensions. For instance, as onenon-limiting example, the widths (W2, W3) could be different for each ofthe first mask openings 147-1, 147-2 due to non-uniformity associatedwith EUV photolithography.

An etching process is performed using the patterned upper layer 146-1(of FIG. 2E) as an etch mask to etch the middle layer 144 and remove theexposed portions of the middle layer 144 and form a patterned middlelayer 144-1 (FIG. 2F). As shown in FIG. 2F, the portions of the middlelayer 144 not covered by the patterned upper layer 146-1 are etched toform the patterned middle layer 144-1. The patterned middle layer 144-1includes the second mask openings 148-1, 148-2 that expose portions ofthe bottom layer 142. As shown in FIG. 2F, the second mask openings148-1, 148-2 are aligned with the first mask openings 147-1, 147-2 (ofFIG. 2E). In some embodiments, the pattern of the patterned upper layer146-1 with the first mask openings 147-1, 147-2 is transferred to thepatterned middle layer 144-1 through the etching process. Therefore, insome embodiments, after the etching process, the patterned middle layer144-1 with the second mask opening 148-1, 148-2 has same pattern as thepatterned upper layer 146-1.

In some embodiments, the etching process used to remove the exposedportions of the middle layer 144 is a dry etch process. In someembodiments, the dry etch process uses oxygen plasma, carbon dioxideplasma, another suitable plasma, or a combination thereof. In some otherembodiments, the etching process that is applied to remove exposedmaterial of the middle layer 144 (i.e., that is not covered by thepatterned upper layer 146-1) is a dry etching process using etchant(s)including CF₄, C₃F₈, C₄F₈, CHF₃, and/or CH₂F₂. In some embodiments, theetching process is a reactive ion etching process, a plasma etchingprocess, any other applicable etching process, or a combination thereof.During the etching process, or as part of a separate removal process,the patterned upper layer 146-1 may also be removed.

Another etching process is performed using the patterned middle layer144-1 (of FIG. 2F) as an etch mask to etch the bottom layer 142 andremove the exposed portions of the bottom layer 142 to form a patternedbottom layer 142-1, as shown in FIG. 2G. For example, the exposedportions of the bottom layer 142 (that are not covered by the patternedmiddle layer 144-1) are etched through the second mask openings 148-1,148-2 to form the patterned bottom layer 142-1 (as shown in FIG. 2G).The patterned bottom layer 142-1 includes third mask openings 148-1′,148-2′ that are separated by an isolation feature positioned between thethird mask openings 148-1′, 148-2′. The third mask openings 148-1′,148-2′ expose portions of first oxide layer 132-1. In some embodiments,the pattern of the patterned middle layer 144-1 is transferred to thepatterned bottom layer 142-1 through the etching process, such that thethird mask openings 148-1′, 148-2′ are aligned with the second maskopenings 148-1, 148-2. In some embodiments, the etching process used toetch the bottom layer 142 is a dry etch process. In some embodiments,the dry etch process uses oxygen plasma, carbon dioxide plasma, anothersuitable plasma, or a combination thereof. In some embodiments, theetching process is a reactive ion etching process, a plasma etchingprocess, any other applicable etching process, or a combination thereof.During the etching process, or as part of a separate removal process,the patterned middle layer 144-1 may also be removed.

As shown in FIG. 2H, an etching process is performed using the patternedbottom layer 142-1 as an etch mask to etch and remove exposed portionsof the first oxide layer 132-1 and underlying portions of the dielectriclayer 114 to thereby extend the third mask openings 148-1′, 148-2′ intothe dielectric layer 114 and form first via openings 149-1, 149-2. Insome embodiments, parameters of the etching process are controlled suchthat the first via openings 149-1, 149-2 extend partially into, but notthrough the dielectric layer 114. As shown in FIG. 2H, the portions ofthe first oxide layer 132-1 not covered by the patterned bottom layer142-1 are etched to expose underlying portions of the dielectric layer114 and the etching process continues to a controlled depth into thedielectric layer 114. As a result, the etching process forms a patternedfirst oxide layer 132-1 and a patterned dielectric layer 114-1. As shownin FIG. 2H, the first via openings 149-1, 149-2 are aligned with thethird mask openings 148-1′, 148-2′, and separated by an isolationfeature positioned between the first via openings 149-1, 149-2. In someembodiments, the etching process is a dry etch process. In someembodiments, the dry etch process uses oxygen plasma, carbon dioxideplasma, another suitable plasma, or a combination thereof. In some otherembodiments, the etching process is a reactive ion etching process, aplasma etching process, any other applicable etching process, or acombination thereof. In some embodiments, during the etching process, oras part of a separate removal process, the patterned bottom layer 142-1may also be removed.

As shown in FIG. 2I, a removal process can be performed to remove theremaining portions of the patterned bottom layer 142-1. In someembodiments, the patterned bottom layer 142-1 can be removed by using anashing process or stripping process. In some embodiments, the ashingprocess uses oxygen plasma, carbon dioxide plasma, another suitableplasma, or a combination thereof. As shown in FIG. 2I, the remainingmask elements of the patterned hard mask 130-1, which include theremaining portions 138-1 of the first trench 138 (of FIG. 2I), form anetch mask structure that serve as an etch mask during subsequent etchingsteps.

As shown in FIG. 2J, another dry etching process can then be performedwith the remaining mask elements of the patterned hard mask 130-1serving as an etch mask. In this dry etching process, the remainingportions 138-1 of the first trench 138 (of FIG. 2I) can be furtherextended into the dielectric layer 114. This dry etching process alsoremoves at least some portions of the remaining mask elements of thepatterned hard mask 130-1. For example, in some embodiments, asillustrated in FIG. 2J, this dry etching process also removes theremaining portions 136-1 of the second oxide layer 136, and partiallyetches the remaining portions 134-1 of hard mask layer 134 and portionsof the first oxide layer 132 (e.g., so that they have a concaveprofile). The dry etching process also partially etches portions of thedielectric layer 114 that underlie the trench 138-1 to form a trench 160that extends deeper into the patterned dielectric layer 114-1. As alsoshown, this dry etching process also removes portions of the second etchstop layer 112 that underlie the first via openings 149-1, 149-2 (shownin FIG. 2I) so that second via openings 150-1, 150-2 extend through thesecond etch stop layer 112 and to the first etch stop layer 110, wherethe etching process stops. In this regard, the dry etching process usedin FIG. 2J to extend the trench 160 into the dielectric layer 114 and toextend the second via openings 150-1, 150-2 to the first etch stop layer110 may also include a wet etching process in some embodiments.

As shown in FIG. 2K, a wet etching process can then be performed toremove exposed portions of the first etch stop layer 110 so that thethird via openings 152-1, 152-2 extend through the first etch stop layer110 to the conductive features 108. In other words, the portions of thefirst etch stop layer 110 exposed by the third via openings 152-1, 152-2are etched so that the third via openings 152-1, 152-2 extend throughthe etch stop layer 110 and expose a surface of the conductive features108. In other embodiments, a dry etching process can be applied incombination with the wet etching process.

As shown in FIG. 2L, a barrier layer 188 can then be conformallydeposited so that it over the remaining portions of the dielectric layer114 and the third via openings 152-1, 152-2. The barrier layer 188conformally covers the top surface of the material layer 102, thesidewalls of the material layer 102 exposed by the trench 160 and thethird openings 152-1, 152-2. In some embodiments, the barrier layer 188is made of a metal nitride such as TaN, TiN, WN, TbN, VN, ZrN, CrN, WC,WN, WCN, NbN, MN, and combinations thereof. In some embodiments, thebarrier layer 188 includes a Ta/TaN bi-layer structure. In someembodiments, the barrier layer 188 is deposited by using physical vapordeposition (PVD), chemical vapor deposition (CVD), plasma enhancedchemical vapor deposition (PECVD), or plasma enhanced atomic layerdeposition (PEALD), other applicable processes, or a combinationthereof.

As shown in FIG. 2M, a conductive layer 190 can then be deposited overthe diffusion barrier layer 188 to fill the second trench 160 and thirdvia openings 152-1, 152-2. The conductive layer 190 may include a seedlayer, which is not shown in figures for the purpose of simplicity andclarity. The barrier layer 188 is positioned between the conductivelayer 190 and other parts of the material layer 102 and/or thesemiconductor substrate 101 so as to prevent metal diffusion from theconductive layer 190 into the material layer 102 and/or thesemiconductor substrate 101. In some embodiments, the conductive layer190 is made of or includes copper, aluminum, tungsten, titanium, cobalt,tantalum, gold, chromium, nickel, platinum, iridium, rhodium, an alloythereof, another conductive material, or a combination thereof. In someembodiments, the conductive layer 190 is deposited using anelectroplating process, a PVD process, a CVD process, an electrolessplating process, one or more other applicable processes, or acombination thereof.

As shown in FIG. 2N, a planarization process can be performed to removeportions of the conductive layer 190 overlying and outside of the secondtrench 160, portions of the diffusion barrier layer 188, and theremaining portions 134-2 of the hard mask layer 134 and remainingportions 132-2 of the oxide layer 132 until portions of the dielectriclayer 114 are exposed. The planarization process may include a chemicalmechanical polishing (CMP) process, a dry polishing process, a grindingprocess, an etching process, one or more other applicable processes, ora combination thereof.

Following the planarization process, conductive features 190, 192-1,192-2 are confined in remaining portions of the dielectric layer 114.The remaining portions of the conductive layer 190 form conductivefeatures 190, 192-1, 192-2 of interconnect structure 195. Conductivefeature 190 is electrically connected to the conductive features 108through the conductive features 192-1, 192-2. The conductive feature 190that remains in the trench 160 may form a structure that is referred toas a conductive interconnect line, and the conductive features 192-1,192-2 that contact conductive features 108 may be referred to asconductive vias. The conductive features 192-1, 192-2 may havesubstantially the same width or different widths. For example, one ofthe conductive features 192-1 may be wider than the other conductivefeature 192-2.

Following fabrication of the interconnect structure 195 illustrated inFIG. 2N, one or more dielectric layers and multiple conductive featuresmay be formed over the dielectric layer 114 and the conductive features190, 192-1, 192-2 to continue the formation of the interconnectionstructure of the semiconductor device structure, as shown in onenon-limiting example that will be described with reference to FIG. 3 .

FIG. 3 is a cross-sectional view that illustrates differentback-end-of-line interconnect layers 310 of an integrated circuitarchitecture 300 where interconnect structures fabricated in accordancewith FIGS. 1 and 2A-2N may be integrated in accordance with someembodiments. As shown in FIG. 3 , conductive features 108 of FIG. 2N maybe part of a metal zero (M0) layer 102, and the conductive features 190,192-1, 192-2 may be, for example, part of a metal one (M1) interconnectlayer. In some embodiments, the steps illustrated in FIGS. 2A-2N arerepeated one or more times to continue the formation of additionalinterconnection structures in a metal two (M2) interconnect layer orhigher. For example, one or more etch stop layers, which may be the sameas or similar to the first etch stop layer 110 and second etch stoplayer 112, may be deposited to cover the dielectric layer 114 shown inFIG. 2N and the interconnect structure 195. Afterwards, the same orsimilar steps as those described in FIGS. 2A-2N are performed over theupper etch stop layer (not illustrated) to produce interconnectstructures similar to that illustrated in FIG. 2N in a metal two (M2)layer. The same or similar steps as those described in FIGS. 2A-2N canthen be repeated again to produce interconnect structures similar tothose illustrated in FIG. 2N in other metal layers, which are shown asinterconnect layers 3 through 9 in FIG. 3 for illustrative purposes, butare not limited to interconnect layers 3 through 9. In otherimplementations, additional interconnect layers could be provided.

The steps described in FIGS. 2A-2N describe what is commonly referred toas a via-first dual damascene process for fabricating an interconnectstructure, but are not necessarily limited to being used in a via-firstdual damascene process. For instance, the embodiments of the disclosuremay also be applied to a single damascene process for fabricating theinterconnect structure.

As explained above, the conductive features 108 formed in material layer102 have very small critical dimensions. When fabricating interconnectstructures having vias that need to contact these conductive features108, the small critical dimensions of the conductive features 108 canmake it very challenging to form via openings that extend through thedielectric layer 114 to the conductive features 108. One approach fordoing so is to use advanced EUV lithography technologies that involvemultiple patterning steps so that the via openings can be opened throughthe dielectric layer 114 and reach the conductive features. Thesemultiple patterning steps typically involve multiple mask layers andetching steps to pattern via openings. A hard mask is usually formedover the dielectric layer 114 to prevent damage to the dielectric layer114.

As explained above, when a metal nitride hard mask (e.g., TiN hard maskor the like) is used etching by-products are generated due to reactionsbetween etchants gas and the hard mask material that is being etched. Ithas been observed that these etching by-products can be deposited andaccumulate on surfaces of the dielectric layer 114 during subsequentetching process in the small and narrow via openings and/or along thetrench. As the critical dimensions of the via openings get smallerduring the process of forming the via openings, this can cause underetching problems to occur during subsequent etching steps. This isbecause the fluorinated etching by-products have relatively high-boilingpoints (e.g., relatively low volatility), which, as explained above, cancause an under etching problem to occur during the process of formingthe via openings.

To explain further, when etching a dielectric material, acarbonfluoro-containing etching gas (e.g., CF₄, C₄F₈, etc.) is usuallyapplied, and the reaction between this etching gas and the hard maskmaterial can result in etching by products being generated. For example,when a TiN hardmask is used, a titanium fluoride (TiF_(x)) by-product isgenerated. The titanium fluoride (TiF_(x)) by-product is metallic andhas relatively high boiling point that causes it to accumulate in andblock the via openings, which in turn, can result in under-etching ofthe via openings. This is especially true as the critical dimensions ofthe vias, and hence the via openings shrink and get smaller because thetitanium fluoride (TiF_(x)) by-products fill up more of the via openingsdue to the fact that these by-products have a relatively high boilingpoint. As a result of this blockage, under-etching of the via openingscan occur.

If under etching is left unaddressed, the vias that are eventuallyformed in the under etched via openings have degraded electrical contactwith the conductive feature that they contact. For example, in somecases, this can result in a via that exhibits poor quality of contactwith the conductive feature (e.g., a via that has poor performance). Inan extreme case, this can result in a via that does not contact theconductive feature at all (e.g., a via that is inoperable). In eithercase, if under etching is not addressed, the quality of the via isnegatively impacted.

In accordance with the disclosed embodiments, a hard mask that is formedover the dielectric layer 114 can include a tungsten-based material orlayer. This can be advantageous in comparison to using otherconventional types of hard masks, such as, metal nitride hard masks,because etching by-products, that are generated during various etchingsteps, have a lower boiling point and do not tend to block the viaopenings that are being etched. To explain further, when a hard maskthat comprises a tungsten-based material is used, tungsten fluoride(WF_(x)) etching by-products are produced that have a lower boilingpoint than the etching by-products produced when another material, liketitanium nitride (TiN), is used as the hard mask. Due to lower boilingpoint of tungsten fluoride, the etching by-products do not tend toaccumulate in the via openings. As a result, under etching problems canbe greatly reduced or eliminated.

For example, this can greatly reduce or prevent under etching issuesthat may otherwise occur during subsequent etching steps (e.g., whenattempting to open the first via openings 149-1, 149-2 so that theyextend to the second etch stop layer 112). Because under etching issuesare reduced or eliminated, the resulting second via openings 150-1,150-2 (shown in FIG. 2J) are improved, which in turn, improves the thirdvia openings 152-1, 152-2 (FIG. 2K) that are formed to reach theunderlying conductive features 108. This is particularly beneficial incases where the mask openings, via openings, and conductive features 108have small dimensions (e.g., widths between 5 to 20 nanometers such aswidths between 8 and 13 nanometers).

One option for addressing under etching would be to perform additionaletching steps, but this would add complexity to the fabrication sequencein order to extend via opening to reach the conductive feature. Inaddition, additional etch stop layers would be required, which would addeven more complexity to the overall fabrication sequence. As such,another advantage of the disclosed embodiments is that because underetching is no longer a concern, the number of etching steps that areneeded can be reduced. As such, the number of etch stop layers that areneeded can be reduced in comparison to other approaches where underetching is a concern, which can further simplify the over fabricationsequence used to form the interconnect.

In some embodiments, methods are provided for forming a semiconductordevice structure. In accordance with these methods, a first etch stoplayer is formed overlying a semiconductor structure having a conductivefeature formed therein, and a second etch stop layer is formed overlyingthe first etch stop layer. A dielectric layer is formed overlying thesecond etch stop layer. A hard mask, that comprises a tungsten-basedmaterial, is formed overlying the dielectric layer, and patterned tocreate a patterned hard mask. In some embodiments, the tungsten-basedmaterial comprises tungsten carbide. In some embodiments, thetungsten-based material comprises tungsten nitride.

A resist layer is formed over the patterned hard mask, and patterned toform a patterned resist layer. Using the patterned resist layer as amask, a first etching process is performed to form a via opening thatextends partially through the dielectric layer. Using the patterned hardmask as an etch mask, a second etching process is performed to extendthe via opening through the second etch stop layer, and a third etchingprocess can be performed to extend the via opening through the firstetch stop layer to reach the conductive feature. In some embodiments,the second etching process is a dry etching process, and the thirdetching process is a wet etching process. In some embodiments, themethod further includes filling the via opening with a conductivematerial to form a via in the dielectric layer.

In some embodiments, the resist layer comprises a multi-layer resistlayer that comprises an upper layer, a middle layer, and a bottom layer.In some embodiments, the resist layer can be patterned to form thepatterned resist layer by performing a first set of etching processes toform a patterned bottom layer. In some embodiments, the first etchingprocess uses the patterned bottom layer as a mask to form the viaopening that extends partially through the dielectric layer.

In some embodiments, the patterning of the hard mask includes patterninga trench in the hard mask to create the patterned hard mask. In someembodiments, the second etching process uses the patterned hard mask asan etch mask to extend the trench further into the dielectric layer andto extend the via opening through the second etch stop layer.

In some embodiments, other methods are provided for forming asemiconductor device structure. In accordance with these methods, afirst etch stop layer is formed overlying a semiconductor structurehaving a conductive feature formed therein, and a second etch stop layeris formed overlying the first etch stop layer. A dielectric layer isformed overlying the second etch stop layer. A hard mask, that comprisesa tungsten-based material, is formed overlying the dielectric layer, andpatterned to create a patterned hard mask. In some embodiments, thetungsten-based material comprises tungsten carbide. In some embodiments,the tungsten-based material comprises tungsten nitride.

A multi-layer resist layer, that includes a bottom layer, is formed overthe patterned hard mask, and a first set of etching processes areperformed to pattern the multi-layer resist layer to create a patternedbottom layer. A first etching process is performed, using the patternedbottom layer as a mask, to form a via opening that extends partiallythrough the dielectric layer. A second etching process is performed,using the patterned hard mask as an etch mask, to extend the via openingthrough the second etch stop layer, and a third etching process isperformed to extend the via opening through the first etch stop layer toreach the conductive feature. In some embodiments, the method furtherincludes filling the via opening with a conductive material to form avia in the dielectric layer that electrically contacts the conductivefeature.

In some embodiments, the patterning of the hard mask includes patterninga trench in the hard mask to create the patterned hard mask.

In some embodiments, the second etching process is performed, using thepatterned hard mask as an etch mask, to extend the trench further intothe dielectric layer and to extend the via opening through the secondetch stop layer. In some embodiments, the second etching process is adry etching process and the third etching process is a wet etchingprocess.

In some embodiments, other methods are provided for forming asemiconductor device structure. In accordance with these methods, asemiconductor structure is provided having at least one conductivefeature formed therein. A first etch stop layer is formed overlying asemiconductor structure having a conductive feature formed therein, anda second etch stop layer is formed overlying the first etch stop layer.A dielectric layer is formed overlying the second etch stop layer.

An interconnect structure is formed in the dielectric layer. Theinterconnect structure can be formed by forming a hard mask overlyingthe dielectric layer, wherein the hard mask comprises a tungsten-basedmaterial; patterning a trench in the hard mask to create a patternedhard mask; forming a multi-layer resist layer over the patterned hardmask, wherein the multi-layer resist layer comprises an upper layer, amiddle layer, and a bottom layer; performing a first set of etchingprocesses to pattern the multi-layer resist layer to form a patternedbottom layer; performing another etching process a second set of etchingprocesses, using the patterned bottom layer as a mask, to form a viaopening that extends partially through the dielectric layer; performinga dry etching process, using the patterned hard mask as an etch mask, toextend the trench further into the dielectric layer and to extend thevia opening through the second etch stop layer; performing a wet etchingprocess to extend the via opening through the first etch stop layer toreach the conductive feature; and filling the via opening and the trenchwith a conductive material to form the interconnect structure in thedielectric layer, wherein the interconnect structure electricallycontacts the conductive feature. In some embodiments, the tungsten-basedmaterial comprises tungsten carbide. In some embodiments, thetungsten-based material comprises tungsten nitride.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method for forming a semiconductor devicestructure, the method comprising: forming a first etch stop layeroverlying a semiconductor structure having a conductive feature formedtherein; forming a second etch stop layer overlying the first etch stoplayer; forming a dielectric layer overlying the second etch stop layer;forming a hard mask overlying the dielectric layer, wherein the hardmask comprises a tungsten-based material; patterning the hard mask tocreate a patterned hard mask; forming a resist layer over the patternedhard mask; patterning the resist layer to form a patterned resist layer;performing a first etching process, using the patterned resist layer asa mask, to form a via opening that extends partially through thedielectric layer; performing a second etching process, using thepatterned hard mask as an etch mask, to extend the via opening throughthe second etch stop layer; and performing a third etching process toextend the via opening through the first etch stop layer to reach theconductive feature.
 2. The method as claimed in claim 1, wherein thetungsten-based material comprises tungsten carbide.
 3. The method asclaimed in claim 1, wherein the tungsten-based material comprisestungsten nitride.
 4. The method as claimed in claim 1, wherein forming aresist layer, comprises: forming a multi-layer resist layer over thepatterned hard mask, wherein the multi-layer resist layer comprises anupper layer, a middle layer, and a bottom layer.
 5. The method asclaimed in claim 4, wherein patterning the resist layer to form apatterned resist layer comprises: performing a first set of etchingprocesses to pattern the multi-layer resist layer to form a patternedbottom layer.
 6. The method as claimed in claim 5, wherein performingthe first etching process to form the via opening that extends partiallythrough the dielectric layer, comprises: performing the first etchingprocess, using the patterned bottom layer as a mask, to form the viaopening that extends partially through the dielectric layer.
 7. Themethod as claimed in claim 1, wherein patterning the hard mask to createa patterned hard mask, comprises: patterning a trench in the hard maskto create the patterned hard mask.
 8. The method as claimed in claim 7,wherein performing the second etching process, comprises: performing thesecond etching process, using the patterned hard mask as an etch mask,to extend the trench further into the dielectric layer and to extend thevia opening through the second etch stop layer.
 9. The method as claimedin claim 8, wherein the second etching process is a dry etching processand wherein the third etching process is a wet etching process.
 10. Themethod as claimed in claim 1, further comprising: filling the viaopening with a conductive material to form a via in the dielectriclayer.
 11. A method for forming a semiconductor device structure, themethod comprising: forming a first etch stop layer overlying asemiconductor structure having a conductive feature formed therein;forming a second etch stop layer overlying the first etch stop layer;forming a dielectric layer overlying the second etch stop layer; forminga hard mask overlying the dielectric layer, wherein the hard maskcomprises a tungsten-based material; patterning the hard mask to createa patterned hard mask; forming a multi-layer resist layer over thepatterned hard mask, the multi-layer resist layer comprising a bottomlayer; performing a first set of etching processes to pattern themulti-layer resist layer to create a patterned bottom layer; performinga first etching process, using the patterned bottom layer as a mask, toform a via opening that extends partially through the dielectric layer;performing a second etching process, using the patterned hard mask as anetch mask, to extend the via opening through the second etch stop layer;and performing a third etching process to extend the via opening throughthe first etch stop layer to reach the conductive feature.
 12. Themethod as claimed in claim 11, wherein the tungsten-based materialcomprises tungsten carbide.
 13. The method as claimed in claim 11,wherein the tungsten-based material comprises tungsten nitride.
 14. Themethod as claimed in claim 11, wherein patterning the hard mask tocreate a patterned hard mask, comprises: patterning a trench in the hardmask to create the patterned hard mask.
 15. The method as claimed inclaim 14, wherein performing the second etching process, comprises:performing the second etching process, using the patterned hard mask asan etch mask, to extend the trench further into the dielectric layer andto extend the via opening through the second etch stop layer.
 16. Themethod as claimed in claim 15, wherein the second etching process is adry etching process and wherein the third etching process is a wetetching process.
 17. The method as claimed in claim 11, furthercomprising: filling the via opening with a conductive material to form avia in the dielectric layer that electrically contacts the conductivefeature.
 18. A method for forming a semiconductor device structure, themethod comprising: providing a semiconductor structure having at leastone conductive feature formed therein; forming a first etch stop layeroverlying the semiconductor structure; forming a second etch stop layeroverlying the first etch stop layer; forming a dielectric layeroverlying the second etch stop layer; and forming an interconnectstructure in the dielectric layer, wherein forming the interconnectstructure comprises: forming a hard mask overlying the dielectric layer,wherein the hard mask comprises a tungsten-based material; patterning atrench in the hard mask to create a patterned hard mask; forming amulti-layer resist layer over the patterned hard mask, wherein themulti-layer resist layer comprises an upper layer, a middle layer, and abottom layer; performing a first set of etching processes to pattern themulti-layer resist layer to form a patterned bottom layer; performinganother etching process, using the patterned bottom layer as a mask, toform a via opening that extends partially through the dielectric layer;performing a dry etching process, using the patterned hard mask as anetch mask, to extend the trench further into the dielectric layer and toextend the via opening through the second etch stop layer; performing awet etching process to extend the via opening through the first etchstop layer to reach the conductive feature; and filling the via openingand the trench with a conductive material to form the interconnectstructure in the dielectric layer, wherein the interconnect structureelectrically contacts the conductive feature.
 19. The method as claimedin claim 18, wherein the tungsten-based material comprises tungstencarbide.
 20. The method as claimed in claim 18, wherein thetungsten-based material comprises tungsten nitride.